The D flip flop shown above is very much different from what we have learnt so far. We have designed it using Nand nor or some other basic gates. But this is completely different.
You can also see that the circuit is like cascading of two similar blocks. Block one includes M1, M2 and the first 2 inverters. The rest of the circuit is the repetition of the first part.
Now, why all this unnecessary fuss? Just to make our life simple. If we draw the first part, then we just need to do our Ctrl+C and Ctrl+V to get the second part. As simple as that.
Back to business: As you can see in the schematic, the circuit involves only two basic elements. An nMOS and an inverter. Basically you need to draw only these two and half of your headache is over. (No kidding, I swear J )
The first step is of course opening the Microwind.
From the palette click on the Moss generator and click Generate device. Check the lambda box (bottom right). Make the Width MOS equal to 4. Now click on Generate device. Click bindass at any place on the screen. We get an nMOS.
You can see that the clock which we are using is of two types. One is clk and the next is its complement. That is clk_bar. For that we need an extra inverter. (Other than the four visible). I won’t be showing you how to draw and inverter. You can refer to the previous tutorial to get the idea regarding that. We will be directly inserting it. (Cool eh?).
Go to file>Insert Layout. Browse to the previously drawn inverter and here you are.
You should be able to see the screen somewhat like this:
Insert another inverter. This is Inv 1. You can refer the schematic. This inverter is connected to the output of the nMOS M1.
We need to name them as we draw. This will make lesser confusions.
Half the work is over. The only thing that we need to do is placing them properly. Copying and pasting them on the right area in the right manner. You owe me a treat for this simplicity.
We will be drawing everything in a single well. This will reduce the delay and make it a best choice for the counters and register designs.
We need to take a little care now. Remember that we need to maintain a minimum of 4 lambda distance between adjacent metal rails.
So, be little careful while placing. Keep doing DRC at each step to make sure that you haven’t ended up doing it wrong.
The layouts placing:
- Place the Inverter for inverting the clock at extreme left. (It’s not visible in the schematic, but we need to draw it for inverting the clock and getting clk_bar.
- Now, everything else will be according to the schematic. Place a pass transistor, i.e. an nMOS (M1) at a distance of 4λ from the inverter.
- To the right of this MOS, we have another inverter named Inv 1. Place it at a distance of 4λ from it. Please make sure that all nMOS and pMOS are at the same level.
- The output of this Inv 1 inverter is connected to the input of Inv 2 inverter. So we need to place Inv 2 to the right of Inv 1 at a distance of 4λ. (If you are getting confused scroll up and see the schematic)
- The output of Inv2 is connected as input to pass transistor M2. So, place a pass transistor nMOS M2 to the right of Inv 2.
At this point the layout should look somewhat like this.
The intermediate file can be found here:
As you can make out, we have just done with placing. We need to connect the devices now. Also note that, we have not drawn the second half. Once we are done with the connection, we will duplicate first half. (Both first and the second stages are identical).
Follow this convention:
The vertical routing should be done with metal 2.
The horizontal routing to be done with metal 1.
Note that you should use Metal 1 to Metal 2 contact to connect to metal 1 and metal 2. (It can be found in the palette)
Care should be taken while connecting a polysilicon layer to metal 2 layers. A polysilicon layer cannot be connected to metal 2 layers directly. First, it has to be connected to metal 1. And then it has to be connected to metal 2.
With the above things in our mind, we will proceed with the connections.
After the connections, the layout will look somewhat like this.
You can even download this intermediate file and analyze it.
It’s time to go for stage 2. Copy the layout, just before first inverter and place it to the right of the existing layout.
This creates the second stage.
Again do the necessary connections and your layout is ready.
The final layout will look similar to this.
You can find the same over here:
The output waveforms looks like this:
You can cascade this layout in the manner you want and create various registers and counters.
Have a great time